Multi-core architecture for video decoding

Multiple international video standards in the market have been developed successfully for many commercial products. This paper proposes a new multimedia core and multi-core architecture for multi-standard video decoding. The proposed multimedia core is based on the 6-stage pipelined dual issue VLIW+SIMD architecture and efficient instructions for video decoding. SMIC 130nm process is used for implementation of the proposed architecture whose approximate gate count is about 130K and runs at 125MHz. The multi-core architecture consisting of eight multimedia cores is efficient for parallel decoding of various video compression formats including MPEG-2, MPEG-4, AVS and H.264/AVC.