DocumentCode
2896441
Title
Parallel hardware objects for dynamically partial reconfiguration
Author
Abel, Norbert ; Grüll, Frederik ; Meier, Nick ; Beyer, Andreas ; Kebschull, Udo
Author_Institution
Kirchhoff Inst. for Phys., Heidelberg
fYear
2008
fDate
8-10 Sept. 2008
Firstpage
563
Lastpage
566
Abstract
Many of todaypsilas software-to-hardware compiler projects try to find dataflow parallelism in a sequential program description and use it to generate parallel running hardware components. In this paper we present a new possibility to do a parallel description based on the combination of object-oriented programming and dynamically partial reconfiguration. Our compiler translates software objects directly to hardware objects, which are running in parallel and can be instantiated and removed dynamically. Furthermore, we focus on parallel inter object communication which allows the hardware objects to communicate in parallel.
Keywords
field programmable gate arrays; object-oriented programming; program compilers; reconfigurable architectures; dynamically partial reconfiguration; field programmable gate arrays; object-oriented programming; parallel hardware objects; sequential program description; software-to-hardware compiler; Dynamic programming; Field programmable gate arrays; Hardware; Java; Object oriented programming; Parallel architectures; Parallel programming; Physics; Program processors; Software design;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on
Conference_Location
Heidelberg
Print_ISBN
978-1-4244-1960-9
Electronic_ISBN
978-1-4244-1961-6
Type
conf
DOI
10.1109/FPL.2008.4630009
Filename
4630009
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