F4: Design of “green” high-performance processor circuits

Energy efficiency today is one of the most important design criteria of high-performance processors for practically every application: whether the final chip dissipates more than 100 Watts for general purpose processing or a few Watts for application processing on a SoC and whether a single or multi core architecture is applied best practice design techniques to achieve high performance at low power are essentially the same. Design targets become more and more challenging with every new technology generation which shows with increasing variability how to keep energy efficiency high in every mode of operation, i.e. sleep, standby, regular, and peak performance. General techniques being applied here are gating, adaptivity, and calibration. Finally, in the future really successful improvements of energy efficiency will bring the dilemma that the classical "flexibility vs. energy conflict" is replaced by a new "energy vs. reliability conflict" due to an increasing rate of transient faults. The objective of this Forum is to present a comprehensive overview of energy efficient optimization methodologies for the different kinds of processors (general purpose / application / embedded SoC, single / multi core processors) and to give exemplary examples. While power optimization generally has to be performed at every design level and architectural components including memories this Forum focuses on micro-architecture, logic and circuit, down to the physical implementation level as well as state-of-the-art clocking and supply techniques. The Forum concludes with an outlook on future options, developments, challenges and issues; possible way-outs will be discussed.