Session 20 overview / wireline: High-speed transceivers & building blocks

Summary form only given. Transceivers designed for very high-speed wireline communication must contend with significant channel loss, crosstalk, and reflections by employing various equalization techniques in the transmitter and receiver. Confronting these challenges becomes even more difficult as data rates increase beyond 10Gb/s and designs become power-constrained. The first four papers in this session describe transceivers that address these concerns. The remaining papers describe key building blocks for next-generation transceivers with a focus on various receive equalizer adaptation techniques and spread-spectrum clock generation for EMI reduction.