DocumentCode
2897802
Title
Error performance and decoder hardware comparison between EG-LDPC and BCH codes
Author
Kim, Jonghong ; Cho, Junho ; Sung, Wonyong
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea
fYear
2010
fDate
6-8 Oct. 2010
Firstpage
392
Lastpage
397
Abstract
Low-density parity-check (LDPC) codes are promising for low code rate applications, however its competitiveness over BCH codes in the high code rate region is not well studied. In this work, we compare the Euclidean geometry (EG) LDPC and BCH codes of the length 1,023, 4,095, and 16,383 that have the code rates of 0.75~0.85. Hard-decision input data are applied to both decoders, and the EG-LDPC codes are decoded using the layered bit-flipping (BF) algorithm. Since the number of needed iterations for LDPC decoding depends on the channel condition, both decoders are designed to have the similar minimum throughput. Not only error performance but also hardware complexity and power consumption of these decoders are compared.
Keywords
channel coding; error correction codes; parity check codes; BCH codes; Euclidean geometry; LDPC codes; bit-flipping algorithm; channel coding; decoders; low density parity check; Complexity theory; Decoding; Hardware; Iterative decoding; Signal to noise ratio; Throughput; BCH codes; Low-density parity-check codes; bit-flipping; layered decoding;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems (SIPS), 2010 IEEE Workshop on
Conference_Location
San Francisco, CA
ISSN
1520-6130
Print_ISBN
978-1-4244-8932-9
Electronic_ISBN
1520-6130
Type
conf
DOI
10.1109/SIPS.2010.5624877
Filename
5624877
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