A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology

Author

Jinsoo Rhim ; Kwang-Chun Choi ; Woo-Young Choi

Author_Institution

Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea

fYear

2012

fDate

4-7 Nov. 2012

Firstpage

104

Lastpage

107

Abstract

This paper reports a 10-Gb/s power and area efficient clock and data recovery circuit implemented in 65-nm CMOS technology. CMOS static circuits are used as much as possible so that the power consumption and the chip area can be minimized. In order to alleviate the supply sensitivity of CMOS static circuits, a supply-regulator is implemented. At 10-Gb/s, the clock and data recovery circuit consumes 5-mW of power and occupies 0.0075mm² of area.

Keywords

CMOS integrated circuits; clock and data recovery circuits; power consumption; power supply circuits; CMOS static circuits; CMOS technology; bit rate 10 Gbit/s; clock and data recovery circuit; power 5 mW; power and area efficiency; power consumption; size 65 nm; supply sensitivity; supply-regulator; CMOS integrated circuits; CMOS technology; Charge pumps; Clocks; Regulators; Solid state circuits; Voltage-controlled oscillators; 65-nm CMOS technology; CMOS static circuits; Clock and data recovery; power and area efficienct;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2012 International

Conference_Location

Jeju Island

Print_ISBN

978-1-4673-2989-7

Electronic_ISBN

978-1-4673-2988-0

Type

conf

DOI

10.1109/ISOCC.2012.6407050

Filename

6407050