DocumentCode
2899282
Title
A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme
Author
Huang, Hong-Yi ; Wu, Sheng-Da ; Tsai, Yi-Jui
Author_Institution
Graduate Inst. of Electr. Eng., Nat. Taipei Univ.
fYear
2007
fDate
27-30 May 2007
Firstpage
2160
Lastpage
2163
Abstract
This work presents a CMOS cycle time-to-digital converter (CDC) integrated circuit utilizing a two-level conversion scheme. The technique that allows the achievement of wide dynamic range is presented. The CDC is based on a multi-phase sampling and vernier delay line (VDL) used in conjunction with a synchronous read-out circuitry. The proposed CDC can provide high resolution with the high conversion rate. The CDC achieves 83.3 MEvents/sec conversion rate and 23-ps resolution, stabilized by the dual DLL. The DNL is less than plusmn 0.34 LSB (23 ps). The INL is plusmn 0.33 LSB.
Keywords
CMOS integrated circuits; analogue-digital conversion; delay lines; readout electronics; 23 ps; CMOS integrated circuit; cycle-time-to-digital converter; multi-phase sampling; read-out circuitry; two level conversion scheme; vernier delay line; Circuits; Clocks; Delay lines; Detectors; Dynamic range; Frequency conversion; Phase detection; Sampling methods; Signal resolution; Thickness measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
1-4244-0920-9
Electronic_ISBN
1-4244-0921-7
Type
conf
DOI
10.1109/ISCAS.2007.378601
Filename
4253099
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