VLSI Implementation of a Reconfigurable Mixed-Signal Finite Impulse Response Filter

Author

Özalevli, Erhan ; Huang, Walter ; Hasler, Paul ; Anderson, David V.

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA

fYear

2007

fDate

27-30 May 2007

Firstpage

2168

Lastpage

2171

Abstract

We present an implementation of a reconfigurable 16-tap finite impulse response filter for post-processing applications. This filter exploits the distributed arithmetic technique for signal processing and floating-gate voltage references for setting tunable analog coefficients. The filter is fabricated in 0.5mum CMOS process, and its order can be increased at the cost of 0.011mm² of die area and 0.02mW of power per tap. Measurement results for low-pass and band-pass filters at 50kHz sampling frequency are presented.

Keywords

CMOS integrated circuits; FIR filters; VLSI; band-pass filters; distributed arithmetic; low-pass filters; mixed analogue-digital integrated circuits; 0.02 mW; 0.5 micron; 50 kHz; CMOS process; VLSI implementation; band-pass filters; distributed arithmetic technique; floating-gate voltage references; low-pass filters; mixed-signal finite impulse response filter; reconfigurable finite impulse response filter; signal processing; tunable analog coefficients; Arithmetic; Band pass filters; CMOS process; Costs; Finite impulse response filter; Frequency measurement; Sampling methods; Signal processing; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378603

Filename

4253101