DocumentCode
2900872
Title
ASIC synthesis cost model
Author
Lewis, Jeff ; Carlson, Steve ; Rau, Jerry
Author_Institution
Synopsys Inc., Mt. View, CA, USA
fYear
1990
fDate
17-21 Sep 1990
Abstract
Following a brief introduction to hardware description language (HDL) synthesis and logic synthesis, the impact of synthesis technology on the various aspects of an ASIC product´s lifecycle is enumerated. An ASIC synthesis cost model is presented along with the various assumptions and associated justification that have been made. A partial empirical test of the model is made via a set of actual design case studies
Keywords
application specific integrated circuits; economics; ASIC; HDL synthesis; IC design; hardware description language; logic synthesis; synthesis cost model; Application specific integrated circuits; Automatic logic units; Circuit synthesis; Circuit testing; Costs; Design optimization; Hardware design languages; Logic design; Logic testing; Production;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/ASIC.1990.186071
Filename
186071
Link To Document