Translinear phase-lock loops

This paper discusses the design and implementation of a current-mode phase-locked loop (PLL) using translinear and log-domain circuits. The paper illustrates the use of `log-domain state space´ design equations for both the synthesis and analysis of the log-domain sub-circuits within the complete PLL architecture. The PLL outlined in this paper comprises the following: a four-quadrant translinear current multiplier for phase detection; a current-mode lead-lag loop filter; a current-controlled log-domain oscillator; a translinear current gain cell to control the level of oscillation; a current amplifier to adjust the overall loop gain of the PLL. In contrast to more conventional state-of-the-art PLLs, the major benefit of a log-domain/translinear implementation is thought to be the potential for wide tuning range under low power supply voltage. Sources of non-ideality within the PLL sub-circuits are discussed, and measured results from a complete translinear PLL are presented