Case study of a high speed three-dimensional graphics chip set

Author

Eisenstadt, Robert E.

Author_Institution

VLSI Technol. Inc., San Jose, CA, USA

fYear

1990

fDate

17-21 Sep 1990

Abstract

Design efforts to implement a 3-D graphics chip set are presented. The set contains designs ranging from a 10000-gate 1.5-micron gate array to a 208-pin, 50000+-gate 1.0-micron silicon compiled design containing RAM and datapath structures. The resulting graphics system contains 85 ASIC chips representing 10 different designs. Overviews of design entry, logic synthesis, physical design, package selection, vector generation, simulation, and test program development are provided. Further information reflecting hardware requirements, and design cycle times is included

Keywords

VLSI; application specific integrated circuits; circuit layout CAD; computer graphic equipment; design engineering; logic arrays; 1 to 1.5 micron; 3-D graphics chip set; ASIC chips; RAM; case study; datapath structures; design cycle times; design entry; gate array; graphics system; hardware requirements; high speed graphics chip set; logic synthesis; package selection; physical design; simulation; test program development; three-dimensional graphics chip set; vector generation; Application specific integrated circuits; Computer aided software engineering; Graphics; Logic arrays; Logic design; Logic testing; Read-write memory; Silicon; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1990.186101

Filename

186101