Title :
1 K×128 high-performance, low power configurable CMOS SRAM compiler
Author :
Le, Toan P. ; Phuong, Hai V. ; Lin, Pei
Author_Institution :
VLSI Technol. Inc., San Jose, CA, USA
Abstract :
A high-density, high-performance, low-power, configurable, fully static RAM compiler is discussed. The compiler can generate different SRAM configurations with a minimum of 128 bits, up to a maximum of 128 K bits. The SRAM has been verified in silicon to have a typical access time of 11 ns (1.0-μm ASIC process) for a 4 K×16 configuration and is functional from 3.5 V to 7.0 V power supply
Keywords :
CMOS integrated circuits; SRAM chips; VLSI; application specific integrated circuits; circuit layout CAD; 11 micron; 11 ns; 128 bit to 128 kbit; 3.5 to 7 V; ASIC memories; SRAM configurations; access time; configurable CMOS SRAM compiler; Application specific integrated circuits; CMOS technology; Ceramics; Costs; Integrated circuit technology; Plastic packaging; Random access memory; Read-write memory; Telecommunications; Very large scale integration;
Conference_Titel :
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1990.186108
