A new method for calculating one-dimensional process margin in consideration of process variations

Author

Miwa, Tadashi ; Noda, Tomonobu ; Akiyama, Tatuo ; Sugimoto, Shigeki

Author_Institution

Semicond. Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan

fYear

1999

fDate

1999

Firstpage

58

Lastpage

61

Abstract

Yield and device characteristics in VLSI become more sensitive to process variations with finer patterns and enlargement of wafer size. Thus, process integration should take account of the inter- and intra-wafer process variations for elimination of yield loss. However, it is difficult to perform experiments which cover possible process variations because of cost and time. In this paper, we describe a new method for calculating a process margin for processes such as etching and deposition with consideration of process variations using the Monte Carlo method

Keywords

Monte Carlo methods; VLSI; etching; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit yield; semiconductor process modelling; 1D process margin calculation method; Monte Carlo method; VLSI; deposition processes; device characteristics; etching; fine patterns; inter-wafer process variations; intra-wafer process variations; process integration; process variations; wafer size; yield characteristics; yield loss elimination; Aluminum; Chemical analysis; Chemical technology; Chemical vapor deposition; Costs; Dielectrics; Etching; Manufacturing processes; Semiconductor device manufacture; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Statistical Metrology, 1999. IWSM. 1999 4th International Workshop on

Conference_Location

Kyoto

Print_ISBN

0-7803-5154-1

Type

conf

DOI

10.1109/IWSTM.1999.773196

Filename

773196