Title :
A pipelined ASIC for color matrixing and convolution
Author :
Hsu, K. ; D´Luna, L.J. ; Yeh, H. ; Cook, W.A. ; Brown, G.W.
Author_Institution :
Dept. of Comput. Eng., Rochester Inst. of Technol., NY, USA
Abstract :
A VLSI chip that can perform either 3×3 matrix multiplication or 3×3 digital convolution is discussed. Built-in self-test (BIST) techniques have been incorporated into the chip to ensure high fault coverage. The chip is designed in a 2-μm CMOS technology using a silicon compiler for physical layout. The device is designed to operate at 14.3 MHz, making it suitable for real-time video and image processing applications
Keywords :
CMOS integrated circuits; VLSI; application specific integrated circuits; built-in self test; circuit layout CAD; computerised picture processing; digital signal processing chips; pipeline processing; real-time systems; special purpose computers; video equipment; 14.3 MHz; 2 micron; 2D convolution; 3×3 matrix; BIST; CMOS; RGB signals; VLSI chip; built in self test; color matrixing; convolution chip; digital convolution; high fault coverage; image processing; matrix multiplication; physical layout; pipelined ASIC; real time processing; silicon compiler; vector multiplication chip; video processing; Algorithm design and analysis; Application specific integrated circuits; Built-in self-test; CMOS technology; Color; Colored noise; Convolution; Image converters; Image processing; Very large scale integration;
Conference_Titel :
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1990.186140
