Title :
Third-generation architecture boosts speed and density of field-programmable gate arrays
Author :
Ravel, Richard B.
Author_Institution :
Xilinx Inc., San Jose, CA, USA
Abstract :
A third-generation family of field-programmable gate arrays (FPGAs) that utilizes a combination of architectural and process improvements and features up to twice the density and speed of currently available FPGA devices is discussed. The architecture allows complete and efficient automated design implementation of FPGA-based designs, as well as maximum density and performance. User-configurable on-chip static memory resources further contribute to the high integration levels available to users of the third-generation devices
Keywords :
circuit CAD; logic CAD; logic arrays; automated design implementation; density; field-programmable gate arrays; on-chip static memory; speed; third-generation family; Boolean functions; CMOS logic circuits; Clocks; Field programmable gate arrays; Logic arrays; Logic devices; Logic programming; Power generation; Routing; Signal generators;
Conference_Titel :
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1990.186197
