Fermi-level pinning at metal/antimonides interface and demonstration of antimonides-based metal S/D Schottky pMOSFETs

Author

Yuan, Z. ; Nainani, A. ; Lin, J.Y. ; Bennett, B.R. ; Boos, J.B. ; Ancona, M.G. ; Saraswat, K.C.

Author_Institution

Dept. Of Elec. Eng., Stanford Univ., Stanford, CA, USA

fYear

2011

fDate

20-22 June 2011

Firstpage

143

Lastpage

144

Abstract

In this paper, we study the metal contact to antimonides compound. Good metal contact formed on p-type material and current suppression on n-type samples is attributed to the Fermi-level pinning at metal/antimonide interface and charge-neutral level being near the valence band edge. Schottky-barrier S/D p-MOSFETs is proposed and experimentally demonstrated which combines an In_xGa_1-xSb channel for good hole transport with metal S/D for low access resistance.

Keywords

Fermi level; III-V semiconductors; MOSFET; Schottky gate field effect transistors; gallium compounds; indium compounds; valence bands; Fermi-level pinning; In_xGa_1-xSb; access resistance; antimonides compound; antimonides-based metal S/D Schottky pMOSFET; charge-neutral level; current suppression; hole transport; metal contact; metal/antimonides interface; n-type samples; p-type material; valence band edge; Annealing; Artificial intelligence; MOSFET circuits; MOSFETs; Ohmic contacts; Temperature measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Device Research Conference (DRC), 2011 69th Annual

Conference_Location

Santa Barbara, CA

ISSN

1548-3770

Print_ISBN

978-1-61284-243-1

Electronic_ISBN

1548-3770

Type

conf

DOI

10.1109/DRC.2011.5994457

Filename

5994457