High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology

In this paper, the mixed-topology full adder chains proposed in (Alioto and Palumbo, 2003) are extensively analyzed versus technology. Analysis aims at exploring the power-delay design space in mixed-topology full adder chains, and evaluating the effect of technology scaling. The mixed-topology approach is also compared with the most representative single-topology circuits for technologies spanning five technology nodes (from 90 nm to 0.35 mum). All circuits are designed at the transistor and the physical level for different design targets, and results account for the layout parasitics. Results demonstrate that the mixed-topology approach is very competitive for every design target, and its advantage over single-topology circuits increases as down-scaling the technology. As a result, the mixed-topology approach is expected to be increasingly appealing when implementing full adder chains in down-scaled technologies.