DocumentCode
290306
Title
RECALS II: a new list scheduling algorithm
Author
Rim, Minjoong ; Jain, Rajiv
Author_Institution
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Volume
ii
fYear
1994
fDate
19-22 Apr 1994
Abstract
Presents a new scheduling heuristic RECALS II for high-level synthesis applications. RECALS II accepts a directed acyclic graph and a set of resources and schedules the graph while minimizing the number of clock cycles required to execute it. Experiments show that schedules produced by RECALS II are close to the optimal solutions
Keywords
circuit CAD; circuit optimisation; computational complexity; data flow graphs; directed graphs; high level synthesis; minimisation; scheduling; RECALS II; clock cycles number; directed acyclic graph; high-level synthesis; list scheduling algorithm; minimization; optimal solutions; resources; scheduling heuristic; Application software; Clocks; Delay; High level synthesis; NP-complete problem; Processor scheduling; Scheduling algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, 1994. ICASSP-94., 1994 IEEE International Conference on
Conference_Location
Adelaide, SA
ISSN
1520-6149
Print_ISBN
0-7803-1775-0
Type
conf
DOI
10.1109/ICASSP.1994.389612
Filename
389612
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