Generating efficient loop code for programmable DSPs

The paper describes research into compilation techniques for modern, off-the-shelf, floating-point DSP devices. These devices offer a high degree of instruction-level parallelism, which is difficult for compilers to exploit effectively. The authors capture the dataflow and vector nature of DSP programs at the source level, and then focus on the application of standard and novel compilation techniques to utilise this parallelism, especially in critical inner loops. The compiler uses an abstract DSP machine and target machine descriptions to model the special features of modern DSPs. This approach facilitates the development of target-independent code generation algorithms. The authors describe in some detail their loop analysis and code generation algorithms