A DSP core for speech coding applications

An application specific processor core for mobile speech coding applications has been designed and implemented. Since the architecture is tailored to the application, it has a very low power consumption, making it attractive for handheld devices. The low power consumption, flexible design and high performance have been achieved by a standby mode, optimized full custom design, and a low clock frequency, together with a highly parallel architecture. All the parallelism is accessible to the user on the assembler level. Engineering samples of the processor have been fabricated and tested. The silicon area required for the core is approximately 25 mm² using 1.0 μm CMOS. A typical average power consumption for a GSM full rate speech codec implementation using this core is less than 50 mW at 5 V operating voltage, and the complex algorithm is executed in less than 5 ms for each 20 ms speech frame (including encode, decode, VAD and DTX operations)