DocumentCode
2903261
Title
Implementation of PBS_LMS algorithm for adaptive filters on FPGA
Author
Majdar, Reza Seifi ; Eshghi, Mohammad
Author_Institution
Fac. of Electr. & Comput. Eng., Shahid Beheshti Univ., Tehran, Iran
Volume
A
fYear
2004
fDate
21-24 Nov. 2004
Firstpage
9
Abstract
In this paper the result of implementing the PBS_LMS algorithm is reported. Transversal adaptive filters for digital signal processing have traditionally been implemented onto DSP processors due to their ability to perform fast floating-point arithmetic operations. Motorola implemented an adaptive filter on ASICS technology (DSP56300). However, with its growing die size as well as incorporating the embedded digital signal processing blocks, the FPGA devices have become a serious contender in the signal processing market. In this paper an adaptive filter is implemented on 2V1500bg575 (Virtex-II family) and on EPIS25F1020C (Stratix family) FPGA from XiIinx and Altera companies. A comparison with this implementation shows a speed about 10:1 with respect to Motorola ASICS is achieved.
Keywords
adaptive filters; digital signal processing chips; field programmable gate arrays; floating point arithmetic; least mean squares methods; 2V1500bg575; ASICS technology; DSP processors; DSP56300; EPIS25F1020C; FPGA; PBS_LMS algorithm; Stratix family; Virtex-II family; adaptive filters; digital signal processing; embedded digital signal processing blocks; floating-point arithmetic operations; parallel binary structured _LMS algorithm; Adaptive filters; Application specific integrated circuits; Digital signal processing; Error correction; Field programmable gate arrays; Floating-point arithmetic; Least squares approximation; Parallel algorithms; Signal processing algorithms; Transversal filters;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 2004. 2004 IEEE Region 10 Conference
Print_ISBN
0-7803-8560-8
Type
conf
DOI
10.1109/TENCON.2004.1414343
Filename
1414343
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