Title :
Leakage-Aware Design of Nanometer SoC
Author :
Kursun, Volkan ; Tawfik, Sherif A. ; Liu, Zhiyu
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI
Abstract :
In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circuit techniques based on multi-threshold-voltage (multi-Vt) and multi-oxide-thickness (multi-tox) standard single-gate and emerging double-gate MOSFET/FinFET technologies are presented in this paper. The leakage savings achieved with the techniques are characterized for a diverse set of logic and memory circuits that are widely used in systems-on-chips. The speed, active power, noise immunity, and area tradeoffs with the leakage reduction schemes are also evaluated.
Keywords :
CMOS logic circuits; CMOS memory circuits; integrated circuit design; leakage currents; nanoelectronics; system-on-chip; CMOS technologies; FinFET; MOSFET; energy reduction; leakage currents; leakage reduction; leakage-aware design; logic circuits; memory circuits; multioxide thickness technology; multithreshold voltage technology; nanometer SoC; systems-on-chips; CMOS logic circuits; CMOS memory circuits; CMOS technology; Energy consumption; FinFETs; Leakage current; Logic circuits; MOSFET circuits; Parasitic capacitance; Threshold voltage;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.378160
