DocumentCode :
2905272
Title :
Analysis of ground bounce in deep sub-micron circuits
Author :
Chang, Yi-Shing ; Gupta, Sandeep K. ; Breuer, Melvin A.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear :
1997
fDate :
27 Apr-1 May 1997
Firstpage :
110
Lastpage :
116
Abstract :
Ground bounce occurs in integrated circuits and can cause signal distortion and increase gate delay. This can result in improper circuit operation. In the past, the switching of input/output buffers was the primary cause of the ground bounce. In designs employing deep sub-micron technology high operating frequency, and short rise/fall times, ground bounce due to switching in internal circuitry becomes a potential problem. In this paper experiments based on realistic assumptions are performed to explore the properties of ground bounce. Experiments indicate that (1) ground bounce is generated in gates, irrespective of whether outputs switch from 0 to 1 or from 1 to 0, (2) ground bounce is reduced when the load capacitance increases, and (3) ground bounce decreases when the number of gates that switch is held constant while the number of gates that don´t switch increases. These conclusions are different from what has been found when input/output buffers switch and lead to new design, verification and test issues
Keywords :
integrated circuit noise; integrated circuit testing; deep sub-micron technology; design; gate delay; gate switching; ground bounce; input/output buffer switching; integrated circuit; internal circuit; load capacitance; signal distortion; simultaneous switching noise; testing; verification; Capacitance; Circuit noise; Distortion; Frequency; Inverters; Latches; Surges; Switches; Switching circuits; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
ISSN :
1093-0167
Print_ISBN :
0-8186-7810-0
Type :
conf
DOI :
10.1109/VTEST.1997.599458
Filename :
599458
Link To Document :
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