DocumentCode :
2906338
Title :
Accelerating FPGA routing using architecture-adaptive A* techniques
Author :
Sharma, Akshay ; Hauck, Scott
Author_Institution :
Actel Corp., Mountain View, CA, USA
fYear :
2005
fDate :
11-14 Dec. 2005
Firstpage :
225
Lastpage :
232
Abstract :
The A* algorithm is a well-known path-finding technique that is used to speed up FPGA routing. Previously published A*-based techniques are either targeted to a class of architecturally similar devices, or require prohibitive amounts of memory to preserve architecture adaptability. This work presents architecture-adaptive A* techniques that require significantly less memory than previously published work. Our techniques are able to produce routing runtimes that are within 7% (on an island-style architecture) and 9% better (on a hierarchical architecture) than targeted heuristic techniques. Memory improvements range between 30× (island-style) and 140× (hierarchical architecture).
Keywords :
field programmable gate arrays; logic design; network routing; FPGA routing; architecture adaptive A*-techniques; heuristic techniques; hierarchical architecture; island style architecture; path finding technique; Acceleration; Costs; Equations; Field programmable gate arrays; Iterative algorithms; Iterative methods; Memory architecture; Routing; Runtime; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN :
0-7803-9407-0
Type :
conf
DOI :
10.1109/FPT.2005.1568551
Filename :
1568551
Link To Document :
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