Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor

As today´s process technologies are combined with steadily increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. The increased chip complexities in combination with the smaller feature sizes requires that we now address defect mechanisms that safely could be more or less ignored in earlier technology nodes. Scan based delay fault testing (AC-scan) fills a large gap in defect coverage as it addresses the dynamic behavior of the circuit under test. Unfortunately, the growing number of scan test vectors may in turn result in costly tester reloads and unacceptable test application times. In this paper we devise a new scan test response compaction scheme based on finite memory compaction (a class of compactors originally proposed in (Rajski, et al.,2003). Our scheme is very diagnosis friendly, which is important when it comes to maintain throughput on the test floor (Stanojevic et al., 2005 and Leininger et al., 2005). Yet, the compactor has comparable performance to other schemes (Rajski et., 2003) when it comes to ´X´ tolerance and aliasing