Title :
An interface protocol component modeling language
Author :
Yun, Chang-Yul ; Jhang, Kyoung-Son
Author_Institution :
Dept. of Comput. Eng., Chungnam Nat. Univ., Taejon, South Korea
Abstract :
Reusing IPs requires designers to perform interface protocol related tasks such as writing test benches and designing interface protocol conversion circuits, e.g, wrappers for IPs. The results of those tasks usually include the interface protocol components for the corresponding IPs, similar to bus protocol components of the bus functional models. Interface protocols of most IPs can be abstracted in transactions. This paper presents a transaction-oriented interface protocol description language which models interface protocol components recognizing or executing transactions over the given interface ports. In addition, we describe a target structure of the synthesizable interface protocol component together with its application to an IP wrapper design. The proposed approach not only reduces re-works on the interface protocol components but also enables the methodology that can be called "transaction-based interface design or synthesis".
Keywords :
circuit simulation; computer interfaces; hardware description languages; industrial property; integrated circuit design; integrated circuit modelling; logic CAD; logic simulation; protocols; transaction processing; BFM; IP reuse; IP wrappers; bus functional models; bus protocol components; interface ports; interface protocol component modeling languages; interface protocol conversion circuits; synthesizable VHDL; test bench writing; transaction-based interface design/synthesis; transaction-oriented interface protocol description language; Circuit synthesis; Circuit testing; Computer interfaces; Design engineering; Hardware design languages; Linear predictive coding; Master-slave; Performance evaluation; Protocols; Writing;
Conference_Titel :
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN :
0-7803-7494-0
DOI :
10.1109/ASIC.2002.1158102