Title :
A new cost-effective morphological filter chip
Author :
Ong, Soohwan ; Sunwoo, Myung H.
Author_Institution :
Sch. of Electr. & Electron. Eng., Ajou Univ., Suwon, South Korea
Abstract :
The paper proposes a new VLSI architecture for morphological filters and presents its design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architectures by using a feedback loop path to reuse partial results and a decoder/encoder pair comparator to detect minimum/maximum values. In addition, the proposed architecture requires one common architecture for both dilation and erosion and a fewer number of operations. Moreover, it can be easily extended for larger size morphological operations. We developed VHDL models, performed logic synthesis using the SYNOPSYSTM CAD tool. We used the 0.8 μm SOG cell library and performed function and timing simulations. The proposed morphological filter chip has been fabricated. The total number of gates is only 2667 and the clock frequency is 30 MHz-that meets real time image processing requirements of the standard of ITU-R BT.601 image format
Keywords :
VLSI; digital signal processing chips; filters; hardware description languages; image processing; logic CAD; real-time systems; 30 MHz; ITU-R BT 601 image format; SOG cell library; SYNOPSYS CAD tool; VHDL models; VLSI architecture; clock frequency; cost effective morphological filter chip; decoder/encoder pair comparator; feedback loop path; hardware costs; larger size morphological operations; logic synthesis; minimum/maximum values; partial results; real time image processing requirements; timing simulations; Costs; Decoding; Feedback loop; Filters; Hardware; Libraries; Logic design; Morphological operations; Timing; Very large scale integration;
Conference_Titel :
Signal Processing Systems, 1997. SIPS 97 - Design and Implementation., 1997 IEEE Workshop on
Conference_Location :
Leicester
Print_ISBN :
0-7803-3806-5
DOI :
10.1109/SIPS.1997.626281