DocumentCode
2906802
Title
An FPGA-based infant monitoring system
Author
Dickinson, Patrick ; Appiah, Kofi ; Hunter, Andrew ; Ormston, Stephen
Author_Institution
Dept. of Comput. & Informatics, Lincoln Univ., UK
fYear
2005
fDate
11-14 Dec. 2005
Firstpage
315
Lastpage
316
Abstract
We have designed an automated visual surveillance system for monitoring sleeping infants. The low-level image processing is implemented on an embedded Xilinx´s Virtex II XC2v6000 FPGA and quantifies the level of scene activity using a specially designed background subtraction algorithm. We present our algorithm and show how we have optimised it for this platform.
Keywords
field programmable gate arrays; image processing; logic design; monitoring; surveillance; Xilinx Virtex II XC2v6000; background subtraction algorithm; field programmable gate array; infant monitoring system; low-level image processing; visual surveillance system; Algorithm design and analysis; Cameras; Field programmable gate arrays; Informatics; Microelectronics; Monitoring; Prototypes; Statistics; Surveillance; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN
0-7803-9407-0
Type
conf
DOI
10.1109/FPT.2005.1568578
Filename
1568578
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