Area-time high level synthesis laws: theory and practice

We introduce three AT DSP high level synthesis laws that relate different components of the area of ASIC implementation cost, namely foreground memory, execution units, and interconnect to the sampling period (available time). The laws state that: A=const, AT=const, and AT ²=const for the area of registers, execution units, and interconnect respectively. We validate the AT laws using case studies and statistical analysis of synthesis results of 80 real life designs. Several applications of the AT laws for development of high level synthesis tools are presented. Use of the AT high level synthesis laws as an effective method for encapsulation of high level synthesis knowledge is also studied, The effectiveness of the AT laws applications is documented on numerous designs