Design and test of FPGA-based direction-of-arrival algorithms for adaptive array antennas

This paper presents the design and parametric testing of two FPGA-based, direction of arrival estimation algorithms (Bartlett and Minimum Variance Distortionless Response) for use in an adaptive array antenna system. The algorithms were implemented on a Xilinx Virtex-5 FPGA and tested using a test bed that emulates signals coming from an 8-channel, circular antenna head after being down converted to an intermediate frequency. The signals are digitized and fed to the FPGA using a custom A/D board. The algorithms were tested while sweeping the incident angle, power level, and single versus dual beams. This paper presents an overview of the digital implementation and the results of the parametric testing.