Analysis of microbump induced stress effects in 3D stacked IC technologies

Author

Ivankovic, A. ; Van der Plas, G. ; Moroz, V. ; Choi, M. ; Cherman, V. ; Mercha, A. ; Marchal, P. ; Gonzalez, M. ; Eneman, G. ; Zhang, W. ; Buisson, T. ; Detalle, M. ; Manna, Antonio La ; Verkest, D. ; Beyer, G. ; Beyne, E. ; Vandevelde, B. ; De Wolf, I. ;

Author_Institution

IMEC, Leuven, Belgium

fYear

2012

fDate

Jan. 31 2012-Feb. 2 2012

Firstpage

1

Lastpage

5

Abstract

Besides the stress around Cu TSV´s, also the stress induced by microbumps is a main contributor to transistor level stress. For complete and successful deployment of 3D IC all effects generating stress have to be addressed. Therefore, this work quantifies the stress and its effects associated with Cu microbumps and their interaction with underfill material in 3D stacks by using a combined experimental and theoretical approach. We report on the stress generated by backside microbumps affecting FETs through the thinned silicon die and the stress on the thin die caused by 3D stacking. We find that the FET current shifts reach over 40% due to the impact of stress. Additionaly, a FEM parametric study was performed to determine key stress reduction contributors in 3D stacks.

Keywords

copper; field effect transistors; finite element analysis; stress effects; three-dimensional integrated circuits; 3D stacked IC technologies; Cu; FEM parametric study; FET current shifts; TSV; backside microbumps; key stress reduction contributors; microbump induced stress effects; thinned silicon die; through silicon vias; transistor level stress; underfill material; Arrays; FETs; Finite element methods; Silicon; Stress; Temperature measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2011 IEEE International

Conference_Location

Osaka

Print_ISBN

978-1-4673-2189-1

Type

conf

DOI

10.1109/3DIC.2012.6262972

Filename

6262972