The reliability and availability analysis of SEU mitigation techniques in SRAM-based FPGAs

Field Programmable Gate Arrays (FPGAs) are becoming an appealing solution in space applications due to their high performance, low cost and flexibility. Unfortunately, reconfigurable SRAM-based FPGAs are extremely susceptible to radiation induced Single Event Upsets (SEUs), especially when COTS components are largely adopted today. SEUs can not be eliminated completely using processing or layout solution, but their destructive effect can be mitigated through fault tolerant design techniques, e.g. redundancy structure, bitstream repair techniques or a combination of them. Meanwhile, the effectiveness of these mitigation techniques should be evaluated before using them in real applications. In this paper, several analytical reliability models are proposed to describe the reliability as well as the availability behavior of these mitigation strategies. These models may help designers to select proper level of protection according to the reliable specification of their system.