A VLSI Implementation of a Digital Hybrid-LNS Neuron

This paper describes the design of a test chip implementation of a multiply and accumulate (MAC) unit for a neural network cell that has been optimized for use with the reactive tabu search (RTS) training algorithm. The neuron has been built using the hybrid-logarithmic number system (hybrid-LNS) instead of traditional fixed-point methods. The performance of the neuron is compared to the original MAC unit that was built and implemented in the TOTEM neural network architecture. The results show that the use of hybrid-LNS arithmetic results in a reduction of over 15% in the layout of the neuron. The use of a "multiplierless" architecture also results in a significant reduction in the power consumed by each neuron while processing data.