A monolithic vernier-based time-to-digital converter with dual PLLs for self-calibration

Author

Chen, Poki ; Zheng, Jia-Chi ; Chen, Chun-Chi

Author_Institution

Dept. of Electron. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei

fYear

2005

fDate

21-21 Sept. 2005

Firstpage

321

Lastpage

324

Abstract

This paper presents a monolithic vernier-based time-to-digital converter with 37.5 ps time resolution and theoretically unlimited input range. A single-stage Vernier delay line is used for both coarse and fine measurement. The operation frequencies of Vernier delay line are stabilized by a novel dual phase-locked loops circuit. The proposed TDC successfully eliminates the element mismatch, input range limitation, external bias adjustment and complicated calibration problems. The measured DNL and INL are plusmn0.2 LSB and plusmn0.35 LSB respectively. The chip size is merely 0.222mm² in a 0.35-mum CMOS process

Keywords

CMOS integrated circuits; convertors; delay lines; phase locked loops; 0.35 micron; 37.5 ps; CMOS process; Vernier-based time-to-digital converter; calibration problems; dual phase-locked loop circuit; element mismatch elimination; external bias adjustment; input range limitation; monolithic time-to-digital converter; single-stage Vernier delay line; Counting circuits; Delay lines; Detectors; Filters; Frequency; Phase detection; Phase locked loops; Ring oscillators; Timing; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Conference_Location

San Jose, CA

Print_ISBN

0-7803-9023-7

Type

conf

DOI

10.1109/CICC.2005.1568670

Filename

1568670