DocumentCode
2908362
Title
A GSM receiver front-end in 65 nm digital CMOS process
Author
Lee, See Taur ; Peng, Solti
Author_Institution
Texas Instrum. Inc., Dallas, TX
fYear
2005
fDate
21-21 Sept. 2005
Firstpage
349
Lastpage
352
Abstract
A highly compact 18.6mA, 1.5V GSM 850MHz receiver front-end implemented in a standard 65 nm digital CMOS process is presented. It achieves 33dB of gain with noise figure of 1.7dB, in-band IIP3 of -9.9dBm and IIP2 greater than 31 dBm. The P1dB is -26.5dBm and the P1dB with -25dBm blocker at 3MHz offset is -23.1dBm. It occupies an area of just 0.43 mm2
Keywords
CMOS digital integrated circuits; UHF integrated circuits; cellular radio; demodulators; integrated circuit noise; low noise amplifiers; mixers (circuits); radio receivers; 1.5 V; 1.7 dB; 18.6 mA; 1dB compression point; 3 MHz; 33 dB; 65 nm; 850 MHz; GSM receiver front-end; I-Q demodulator circuit; LNA circuit; conversion gain; digital CMOS process; mixer circuit; second-order input intercept point; third-order input intercept point; CMOS process; Circuits; Costs; GSM; Inductors; MOS capacitors; Noise figure; Radio frequency; Resistors; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Conference_Location
San Jose, CA
Print_ISBN
0-7803-9023-7
Type
conf
DOI
10.1109/CICC.2005.1568677
Filename
1568677
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