DocumentCode
2908504
Title
A high performance fault tolerant system for on-board signal processing
Author
Ao Shen ; Kang Xia ; Yuzhuo Fu ; Ting Liu ; Jiang Jiang
Author_Institution
Sch. of Micro Electron., Shanghai Jiao Tong Univ., Shanghai, China
fYear
2012
fDate
15-16 Nov. 2012
Firstpage
355
Lastpage
358
Abstract
The conventional techniques in space mission design put great emphasis on system reliability while the performance is usually quite limited, which can barely meet the highly increasing computation demand from nowadays real-time applications. To solve this problem, a High Performance Fault Tolerant System (HPFTS) architecture for on-board signal processing is presented in this paper. This DSP-based system, with specially designed efficient compare-point mechanism and parallel processing scheme, can dynamically adapt its redundancy level according to varying radiation conditions to archive the best overall performance. The evaluation results show that under a correlation function based benchmark test, the proposed HPFTS prototype can provide a potential of high processing capacity with the promise of required reliability.
Keywords
digital signal processing chips; fault tolerance; real-time systems; redundancy; signal processing; DSP-based system; HPFTS architecture; HPFTS prototype; compare-point mechanism; computation demand; correlation function-based benchmark test; high performance fault tolerant system; high processing capacity; on-board signal processing; parallel processing scheme; real-time applications; redundancy level; space mission design; system reliability; Digital signal processing; Fault tolerant systems; Field programmable gate arrays; Parallel processing; Redundancy; compare-point; fault tolerance; high performance; on-board system;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics and Telecommunications (ISETC), 2012 10th International Symposium on
Conference_Location
Timisoara
Print_ISBN
978-1-4673-1177-9
Type
conf
DOI
10.1109/ISETC.2012.6408137
Filename
6408137
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