Application of VHDL in test program development

Writing functional test programs has been a pervasive task since the inception of computer controlled testing in the early seventies. Software tools have been developed, such as simulators and testability analyzers, to assist with the test programming tasks. With the advent of today´s high density circuitry, we have reached a practical application limit in utilizing these vintage tools on today´s products. This paper describes a test programming paradigm based on VHDL and its application in a VHDL-based simulation tool set