The SuperSPARC microprocessor

Author

Blanck, Greg ; Krueger, Steve

Author_Institution

Sun Microsyst. Inc., Mountain View, CA, USA

fYear

1992

fDate

24-28 Feb. 1992

Firstpage

136

Lastpage

141

Abstract

The SuperSPARC microprocessor is a highly integrated, high-performance superscalar SPARC version 8 compatible microprocessor. The authors provide an overview of its internal operation and capabilities. The processor contains an integer unit, a double precision floating point unit, fully consistent instruction and data caches, a SPARC reference memory management unit and a dual-mode bus interface supporting either the SPARC standard MBUS or an interface optimized for connection to a companion second-level cache controller chip. The chip is constructed using Texas Instruments 0.8- mu triple-layer metal BiCMOS technology.<>

Keywords

buffer storage; microprocessor chips; system buses; SPARC reference memory management unit; SPARC standard MBUS; SuperSPARC microprocessor; Texas Instruments; data caches; double precision floating point unit; dual-mode bus interface; fully consistent instruction; high-performance superscalar SPARC version 8 compatible microprocessor; highly integrated; integer unit; internal operation; metal BiCMOS technology; second-level cache controller chip; Clocks; Cost function; Hardware; Instruments; Local oscillators; Logic; Microprocessors; Multiprocessing systems; Protocols; System buses;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '92. Thirty-Seventh IEEE Computer Society International Conference, Digest of Papers.

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-2655-0

Type

conf

DOI

10.1109/CMPCON.1992.186699

Filename

186699