Title :
A VLSI Architecture for Video Coding Based on PDVQ
Author :
Yu-min, LIAO ; Ning-Mei, Yu ; Dong-fang, WANG
Author_Institution :
Xi´´an Univ. of Technol., Xi´´an
Abstract :
In this paper, we propose a algorithm for video encoding based on partition dynamically vector quantization (PDVQ), and a VLSI architecture for implementing it. The proposed algorithm consists of PDVQ and motion estimation based on PDVQ. In addition to get a high compression ratio, the algorithm also reduces the memory size for restoring the reference frame. The implementation was verified in FPGA, It can support real-time application of 720times576 pels at 25 fps when the operation rate is 80 MHz.
Keywords :
VLSI; field programmable gate arrays; motion estimation; vector quantisation; video coding; FPGA; PDVQ; VLSI architecture; field programmable gate array; frequency 80 MHz; motion estimation; partition dynamically vector quantization; video coding; Hardware; Image coding; Motion estimation; PSNR; Partitioning algorithms; Vector quantization; Very large scale integration; Video coding; Video compression; Video sequences;
Conference_Titel :
Integrated Circuits, 2007. ISIC '07. International Symposium on
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-0797-2
Electronic_ISBN :
978-1-4244-0797-2
DOI :
10.1109/ISICIR.2007.4441842
