LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates

System specification of SoCs needs to be supported by quantitative cost models to avoid wrong decisions in this early design phase. For less complex logic structures like for example FIR filters such generic cost models can be derived easily because they base on a simple gate count. For LDPC decoders the influence of the global interconnect between the two basic components of such a decoder complicates the derivation of general cost models. This might be the reason why no accurate cost models are known from literature yet. In this paper generic silicon area, iteration period, and energy cost models of high-throughput LDPC decoders are derived. Those models do not only allow for a decoding-performance vs. hardware-cost trade-off analysis during system specification but can also be used later on to choose a suitable architecture for a certain specification. Finally these models can be used for a fair benchmarking of the implemented decoder.