A second level multiprocessing cache for the i486DX and i860XP processors

Author

Golbert, Adi ; Farrell, Bob ; MacWilliams, Pete ; Sakran, Nabeel ; Silas, Isic

Author_Institution

Intel Corp., Santa Clara, CA, USA

fYear

1992

fDate

24-28 Feb. 1992

Firstpage

338

Lastpage

343

Abstract

The objective of the present work is to be a primer on the 82495/82490 cache. The authors introduce the basic architecture elements of the solution, and describe in detail the motivations for the chosen architecture. The 495/490 cache uses an innovative architecture with frequency scalability in mind. The cache supports the i486 DX and i860 XP processors, working at 50 MHz. A detailed description of the architecture of the 82495 and 82490 is provided. Special emphasis is given to the innovative architecture elements such as the handling of 2-way associative through the MRU (most-recently-used) scheme, and the handling of the multiprocessing MESI protocol in a hierarchy of L1 and L2 caches. Lastly, the authors provide performance results from simulations and system benchmarkings of the 82495/82490 cache.<>

Keywords

buffer storage; memory architecture; performance evaluation; storage management chips; 2-way associative; 50 MHz; 82495/82490 cache; L1 caches; L2 caches; MRU scheme; frequency scalability; i486DX processors; i860 XP processors; most recently used scheme; multiprocessing MESI protocol; second level multiprocessing cache; Central Processing Unit; Computer architecture; Frequency; Microcomputers; Protocols; Random access memory; Scalability; Standards development; System buses; Trademarks;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '92. Thirty-Seventh IEEE Computer Society International Conference, Digest of Papers.

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-2655-0

Type

conf

DOI

10.1109/CMPCON.1992.186735

Filename

186735