Modeling leakage in ASIC libraries

Leakage is one of today´s most important VLSI design issues, and ASIC design tools require accurate library leakage models. Leakage models have been traditionally derived from Spice simulation, but this approach is difficult and inflexible. Further, Spice simulation may not be possible for all IP in the library. We propose a new approach to modeling leakage of ASIC libraries. This approach is simple and flexible, and it is viable for all IP in the library. It requires no Spice simulation, yet its accuracy has been verified in silicon. It has been implemented for our 90nm ASICs