Design guideline for resistive termination of on-chip high-speed interconnects

This paper discusses the resistive termination of on-chip high-performance interconnects. Resistive termination can improve the bandwidth of on-chip interconnects, on the other hands, increases the power dissipation. Therefore a design guideline for resistive termination is necessary. In this paper, we propose a method to determine the termination of on-chip interconnects. The termination derived by the proposed method provides minimum sensitivity to process variation as well as maximum eye-opening in voltage