An Effective Approach For Subtreshold And Gate Leakage Power Estimation Of SRAM

The leakage current in SRAM is the vital factor for the low power processor design. In this paper we develop a fast approach to calculate the total leakage power of SRAM, considering the subthreshold leakage (I_sub) and gate leakage (I_gate).This method is proposed on the SRAM special architecture, using the stack factors as the average factor to compute the I_sub and using the statistical algorithm to estimate the gate leakage power. The method does not need to be much considered on the working state of SRAM and it can be applied without much spice simulation and suitable for SRAM leakage power computing at the different process. We use this method to test a number of SRAM circuits in the 0.18 mum, 0.13 mum, 90 nm and 65 nm technology and demonstrate the accuracy within less than 5% of hspice on average. This technique is much useful for the system designers to estimate the power earlier, and can effectively improve the power management of the processors and shorten the design time.