A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology

Author

Guilar, Nathaniel J. ; Lau, Pak-Kim ; Hurst, Paul J. ; Lewis, Stephen H.

Author_Institution

Dept. of Electr. & Comput. Eng., California Davis Univ., USA

fYear

2005

fDate

18-21 Sept. 2005

Firstpage

633

Lastpage

636

Abstract

A low-power passive switched-capacitor finite-impulse response equalizer with six time-interleaved channels has been fabricated in 0.35μm CMOS. Nonlinear parasitic capacitance scales the equalized output but does not affect the zero locations of the equalizer for a binary or ternary data signal. The equalizer is fully differential with a 4-tap transfer function. The equalizer consumes 19.5 mW at 200 MS/s and occupies an active area of 1.3mm².

Keywords

CMOS integrated circuits; FIR filters; equalisers; network topology; passive filters; switched capacitor filters; transfer functions; 0.35 micron; 19.5 mW; CMOS circuits; FIR equalizer; binary data signal; finite-impulse response equalizer; nonlinear parasitic capacitance; passive switched-capacitor; ternary data signal; time-interleaved channels; time-interleaved topology; transfer function; Circuit topology; Equalizers; Equations; Finite impulse response filter; Intersymbol interference; Parasitic capacitance; Sampling methods; Switches; Switching circuits; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Print_ISBN

0-7803-9023-7

Type

conf

DOI

10.1109/CICC.2005.1568749

Filename

1568749