Dual channel architecture for reliable FPGA high speed serial links

Point-to-point connectivity through FPGA high-speed serial I/O is an important component for many space-based applications. The susceptibility of high-speed transceivers to soft errors is still under investigation and is a matter of concern in reliable point-to-point communications. This work develops a technique to provide full-bandwidth, lossless data transmission across high-speed transceivers in the presence of soft errors. The technique utilizes a redundant channel which can be used if the first channel fails and needs to be repaired. This allows for uninterrupted transmission even in the face of soft errors. The design has been implemented and tested through manual injection of various faults. No system failures occurred under the injection of any combination of tested faults on a single channel thus demonstrating the potential of such a design to protect against soft errors while maintaining high-bandwidth transmission. The cost of this technique is that it consumes 4.7× the area and has a throughput that is 98% that of an unmitigated single-channel design.