DocumentCode
2909694
Title
EMBRACE-SysC for analysis of NoC-based Spiking Neural Network architectures
Author
Pande, Sandeep ; Morgan, Fearghal ; Cawley, Seamus ; McGinley, B. ; Carrillo, Snaider ; Harkin, Jim ; McDaid, Liam
Author_Institution
Bio-Inspired Electron. & Reconfigurable Comput.(BIRC), Nat. Univ. of Ireland, Galway, Ireland
fYear
2010
fDate
29-30 Sept. 2010
Firstpage
139
Lastpage
145
Abstract
This paper presents EMBRACE-SysC, a simulation-based design exploration framework for the EMBRACE mixed signal Network on Chip (NoC)-based hardware Spiking Neural Network (SNN) architecture. EMBRACE-SysC incorporates Genetic Algorithm-based training of SNN applications. Results illustrate the application of EMBRACE-SysC for performance analysis of a NoC-based SNN architecture. The development of EMBRACE-SysC introduces a powerful design exploration framework for EMBRACE architecture development.
Keywords
genetic algorithms; low-power electronics; mixed analogue-digital integrated circuits; network-on-chip; neural nets; EMBRACE-SysC; NoC-based spiking neural network architectures; genetic algorithm; mixed signal network on chip; Computer architecture; Data models; Generators; Hardware; Neurons; Radiation detectors; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
System on Chip (SoC), 2010 International Symposium on
Conference_Location
Tampere
Print_ISBN
978-1-4244-8279-5
Type
conf
DOI
10.1109/ISSOC.2010.5625566
Filename
5625566
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