A Low Voltage, Low Ripple on Chip Hybrid DC-DC Converter

Here we propose a low voltage low ripple hybrid dc-dc converter. In the proposed topology, along with a linear regulator a switching capacitor is used to store and recycle the charge for better power efficiency. Linear regulator is used to reduce the amount of output voltage ripple that comes from the switching capacitor. The output noise is further reduced by introducing a synthesized counter noise through the linear regulator. With this noise reduction technique, for an acceptable output ripple noise, the switching capacitor is reduced to a value which can be implemented on chip. The proposed converter circuit is designed in 0.18 mu process for 3.3 V to 1.25 V conversion. With 950 pF switching capacitor, for 9.5 mA load current and 100 pF load capacitor, peak-peak output voltage ripple is 75 mV and the power efficiency is 77%.