Title :
Interconnecting multiple input and output LAN-s over a high speed gateway
Author :
Chlamtac, Imrich ; Wong, Eric W M
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
The problem of controlling and configuring the high-speed interconnection of multiple-input and multiple-output LANs (local area networks) is studied. An optimal method for controlling traffic flow to minimize packet loss, given a finite buffer space at each LAN, is derived. It is shown that the optimal buffer allocation among the input and the output buffers depends on the relative number of the interconnected input and output LANs. A new approximate analytic model is provided which is shown to be tractable while introducing only small errors. In terms of loss probability, it was found that the optimal gateway control is one that always delays packet transfer from the input queues to the output queues until the last moment, similarly to a single-output LAN interconnection system. However, as opposed to single LAN systems, given a fixed number of buffers, the optimal buffer allocation is to divide buffers between the input and the output queues
Keywords :
LAN interconnection; MIMO systems; buffer storage; delays; optimal control; packet switching; queueing theory; storage allocation; telecommunication congestion control; analytic model; delays; high speed gateway; high-speed interconnection; local area networks; loss probability; multiple-input and multiple-output LANs; optimal buffer allocation; optimal gateway control; packet loss; queues; traffic flow; Bandwidth; Control systems; Interconnected systems; LAN interconnection; Local area networks; Optimal control; Propagation delay; Spine; Throughput; Traffic control;
Conference_Titel :
Communications, 1993. ICC '93 Geneva. Technical Program, Conference Record, IEEE International Conference on
Conference_Location :
Geneva
Print_ISBN :
0-7803-0950-2
DOI :
10.1109/ICC.1993.397225