A new balanced gate for structural testing

Author

Razavi, Hassan M. ; Wong, Paul W.

Author_Institution

North Carolina Univ., Charlotte, NC, USA

fYear

1992

fDate

27-29 May 1992

Firstpage

51

Lastpage

55

Abstract

A new circuit realization is presented for a family of gates that results in a simple test for structural integrity of a CMOS circuit. The gate during normal operation behaves like an ordinary CMOS gate. However, in the test mode a nominal voltage of 2.5 V on the inputs of the gate would result in a 2.5-V output if no stuck-at faults are present. A combinational circuit designed exclusively with this type of a gate can be tested for all stuck-at faults using a single test vector of 2.5 V on all primary inputs. It is shown that a 100% fault coverage is obtained at the gate level (90% at the transistor level) for a combinational circuit regardless of its size, function, and complexity

Keywords

CMOS integrated circuits; combinatorial circuits; integrated logic circuits; logic testing; CMOS circuit; balanced gate; combinational circuit; fault coverage; structural integrity; structural testing; stuck-at faults; Application specific integrated circuits; Circuit faults; Circuit testing; Clocks; Combinational circuits; Integrated circuit manufacture; Integrated circuit testing; Logic testing; Redundancy; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 1992. Proceedings., Twenty-Second International Symposium on

Conference_Location

Sendai

Print_ISBN

0-8186-2680-1

Type

conf

DOI

10.1109/ISMVL.1992.186777

Filename

186777